1. Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to forming an Epitaxial (epi) Source/Drain (S/D) in a fin field effect transistor (FinFET) device.
2. Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., field effect transistors (FETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FET is formed by the intersection of two shapes, a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing, and level definition (e.g., etching, implanting, deposition, etc.).
The FinFET is a transistor design that attempts to overcome the issues of short-channel effect encountered by deep submicron transistors, such as drain-induced barrier lowering (DIBL). Such effects make it harder for the voltage on a gate electrode to deplete the channel underneath and stop the flow of carriers through the channel—in other words, to turn the transistor off. By raising the channel above the surface of the wafer instead of creating the channel just below the surface, it is possible to wrap the gate around all but one of its sides, providing much greater electrostatic control over the carriers within it.
In FinFET technology, both Epitaxial (epi) Source/Drain (S/D) and/or Replacement Metal Gate (RMG) techniques are commonly employed. Epitaxy involves the growth of a crystalline material (e.g., a S/D) on the crystal face of another material (e.g., a finned substrate), in such a manner that the crystalline substrates of both minerals have the same structural orientation. An epi S/D can help to reduce parasitic series resistance.
A replacement metal gate process refers to the formation of a temporary or “dummy” gate in a location where the gate is to be located. This dummy gate is removed after other formation processes have occurred and the gate is formed in the vacated location. This process can help to alleviate challenges that may be present in alternative gate-first integration processes.